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an11054 greenchip iii+ ssl410 1 integrated pfc a nd flyback controller rev. 1 ? 13 may 2011 application note document information info content keywords greenchip iii+, ssl4101, pfc, flyback, high-efficiency, led driver, adapter, notebook, pc power, low thd, high power factor (pf). abstract the ssl4101 is a member of the new generation of combined pfc and flyback controller ics for efficient switched mode power supplies. it has a high level of integration which allows the design of a cost effective power supply with a very low number of external components. the ssl4101 is fabricated in a silicon on insulator (soi) process. the nxp semiconductors soi process makes a wide voltage range possible.
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 2 of 27 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller revision history rev date description v.1 20110513 first issue
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 3 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller 1. introduction the ssl4101 is a combination ic with bo th a power factor controller (pfc) and a flyback controller integrated into an so16 package. both controllers operate in quasi-resonant (qr) or discontinuous conduction mode (dcm) mode with valley detection. switching is independent for each controller. the pfc output power is an on-time controlled for simplicity. it is not necessary to sense the phase of the mains voltage. the flybac k output power is current controlled mode (ccm) ensuring good suppression of the input voltage ripple. the communication circuitry between both controllers is integrated and no adjustment is needed. the voltage and current levels mentioned in this application note are typical values. a detailed description of the pin leve l spreading can be found in the ssl4101 data sheet . 1.1 scope this application note describes the function ality and the control functions of ssl4101 and the adjustments needed within th e power controller application. the design and data for the inductor and transformer for the large signal parts of the pfc and flyback power stages are dealt with in a separate application note. 1.2 the ssl4101 greenchip iii+ controller the features of the greenchip iii+ allow the power supply engineer to design a reliable, cost-effective and efficient switched mode power supply (smps) with the minimum number of external components. 1.2.1 key features ? pfc and flyback controller integrated in one so16 package ? switching frequency of pfc and flyback are independent of each other ? no external hardware required for co mmunication between the two controllers ? high level of integration, resulting in a very low external component count ? integrated mains voltage enable and brown-out protection ? fast latch reset function 1.2.2 system features ? safe restart mode for system fault conditions ? high voltage start-up current source (5.4 ma) ? reduction of hv current source (1 ma) in safe restart mode ? wide v cc range (up to 38 v) ? mosfet driver voltage limited ? easily controlled start-up behavior and v cc circuit ? general purpose input for latched protection ? internal ic overtemperature protection (otp)
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 4 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller ? two high voltage spacers between the hv pin and the next active pin ? open pin protection on the vinsense, vosense, pfcaux, fbctrl and fbaux pins 1.2.3 pfc features ? qr/dcm operation with valley switching ? t on controlled ? mains input voltage compensation of the control loop for good transient response ? overcurrent protection (ocp) ? soft-start and soft-stop ? open/short detection for pfc feedback loop: no external ovp circuit necessary 1.2.4 flyback features ? qr/dcm operation with valley switching ? frequency limitation (125 khz) to reduce switching losses and emi ? current controlled mode (ccm) ? overcurrent protection (ocp) ? frequency reduction with fixed minimum peak current to maintain high-efficiency at low output power levels without audible noise ? soft-start function ? accurate overvoltage protection (ovp) through the auxiliary winding ? time-out protection for output overloads and open flyback feedback loop, available as safe restart
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 5 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller 1.3 application schematic fig 1. application schematic mains inlet 2 4 1 9,10 7,8 97 1 5 5 6 vout gnd c32a r1 lf2 r9 t1 c7 r16 c8 c3 d3 f1 r33 r25 r23a d4 c16 r6 r10 q2 r27 r3 c19 u1 ssl4101 pfcdriver 12 vinsense 7 hvs 14 latch 5 pfccomp 6 fbaux 4 hv 16 fbsense 10 fbdriver 13 vosense 9 hvs 15 pfcsense 11 gnd 2 pfcaux 8 fbctrl 3 vcc 1 cy1 l2 r32 c31 d2 r11 u2 1 2 3 4 c15 u3 c1 c4 r24 c2 cx1 r26 d5 r18 l1 r31 lf1 r13 c14 c37 c13 rt2 r14 c10 r8 q1 r23 + bd1 - r4 r5 c18 c20 d23a c6 r2 r15 r7 r32a r12 d10 c36 d1 c17 r30 r17 019aac320
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 6 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller 2. pin description table 1. pin description pin name functional description 1v cc supply voltage: v startup = 22 v, v th(uvlo) = 15 v. at mains switch-on, the capacitor connected to this pin is charged to v cc start by the internal hv current source. when the pin voltage is lower than 0.65 v, the charge current is limited to 1 ma, this to prevent overheating of the ic if the v cc pin is short circuited. w hen the pin voltage is between 0.65 v and v th(uvlo) , the charge current is 5.4 ma to enable a fast start-up. between v th(uvlo) and v startup , the charge current is again limited to 1 ma, this to reduce the safe restart duty cycle and as a resu lt the input power during fault conditions. at the moment v startup is reached the current source is pinched-off, and v cc is regulated to v startup till the flyback starts. see chapter section 3.2 for a complete description of the start-up sequence. 2 gnd ground connection. 3 fbctrl control input for flyback for dire ct connection of the optocoupler. at a control-voltage of 2 v the flyback will deliver maximum power. at a control voltage of 1.5 v the flyback will enter the frequency reduction mode and the pfc will be switched off. at 1.4 v the flyback will stop switching. internal there is a 30 ma current source connect ed to the pin, which is controlled by the internal logic. this current source can be used to implement a time-out function to detect an open control- loop or a short circuit of the output-voltage. the time-out function can be disabled with a resistor of 100 k between this pin and ground 4 fbaux input from auxiliary winding fo r transformer demagnetization detection, mains dependent overpower protecti on (opp) overvoltage protection (ovp) of the flyback. the combination of the demagnetization detection and the valley detection at pin hv determines the switch-on moment of the flyback in the valley. a flyback ovp is detected at a current > 300 a into the fbaux pin. internal filtering is pr esent to prevent false detection of an ovp. the flyback opp starts at a current 100 a out of the fbaux pin. 5 latch general purpose latched protection input. when v startup (pin 1) is reached, this pin is charged to a voltage of 1.35 v first before the pfc is enabled. to trigger the latched protec tion the pin has to be pulled down to below 1.25 v. an internal 80 a current source is connected to the pin, which is controlled by the internal logic. because of this current source, an ntc resistor for temperature protection can be dire ctly connected to this pin. 6 pfccomp frequency compensation pin for the pfc control loop. 7 vinsense sense input for mains voltage. this pin has 5 functions: ? mains enable level: v start(vinsense) = 1.15 v; ? mains stop level (brown-out): v stop(vinsense) = 0.9 v; ? mains voltage compensation for the pfc control-loop gain bandwidth; ? fast latch reset: v flr = 0.75 v the mains enable and mains stop level will enable and disable the pfc. the voltage at the vinsense pin must be an averaged dc value, representing the ac line voltage. the pin is not used for sensing the phase of the mains voltage. 8 pfcaux input from an auxiliary winding of the pfc coil for demagnetization timing and valley detection to control the pf c switching. the auxiliary winding needs to be connected by a 5 k series resistor to prevent damage of the input due to lightning surges.
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 7 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller 9 vosense sense input for ou tput voltage of the pfc. vosense pin, open loop and short detection: v th(ol)(vosense) = 1.15 v regulation of pfc output voltage: v reg(vosense) = 2.5 v pfc soft-ovp (cycle-by-cycle): v ovp(vosense) = 2.63 v 10 fbsense current sense input for flyback. at this pin, the voltage across the flyback current sense resistor is measured. the setting of the sense level is determined by the fbctrl voltage, using the equation: v fbsense = 0.75 v fbctrl ? 1 v. the maximum setting level for v fbsense = 0.5 v. internal there is a 60 a current source connect ed to the pin, which is controlled by the internal logic. the cu rrent source is used to implement a soft-start function for the flyback and to enable the flyback. the flyback will only start when the internal current source is able to charge the soft-start capacitor to a voltage of more than 0.5 v, therefore a minimum soft-start resistor of 12 k is required to guarantee the enabling of the flyback. 11 pfcsense overcurrent protection input for pfc. this input is used to limit the maximum peak current in the pfc inductor. the pfcsense is a cycle by cycle protection, at 0.5 v the pfc mosfet is switched off. there is an internal 60 a current-source connected to the pin, which is controlled by the internal logic. this current source is used to implement a soft-start and soft-stop function. this pin is also used for enabling of the pfc. the pfc only starts when the internal current source is able to charge the soft-start capacitor to a voltage of more than 0.5 v, therefore a minimum soft-start resistor of 12 k is required to guarantee the enabling of the pfc. 12 pfcdriver gate driver output for pfc mosfet. 13 fbdriver gate driver output for flyback mosfet. 14 hvs high voltage safety spacer, not connected 15 hvs high voltage safety spacer, not connected 16 hv high voltage input for internal start-up current source (output at pin 1), and valley sensing of the flyback. the combination of the demagnetization detection at the fbaux pin and the valley detection at the hv pin are det ermining the switch- on moment of the flyback in the valley. table 1. pin description pin name functional description
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 8 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller 3. system descripti on and calculation 3.1 pfc and flyback start conditions in figure 2 and figure 3 , show the conditions for enabling of the pfc and flyback are given. in case of start-up problems these co ndition can be checked to find the cause of the problem. some of the conditions are dynamic signals (see figure 4 ) and should be checked with an oscilloscope. 3.2 start-up sequence at switch on with a low mains voltage, th e ssl4101t power supply has the following start-up sequence (see figure 4 ): 1. the hv current source is set to 0.9 ma and the v cc elcap is charged to 0.65 v to detect a possible short-circuit on pin vcc. 2. at v cc = 0.65 v, the hv current source is set to 5.4 ma and the v cc elcap is fast charged to v th(uvlo) . 3. at v cc = v th(uvlo) , the hv current source is set to 0.9 ma again and the v cc elcap is charged further to v startup . 4. at v startup , the hv current source is switched off and the 80 a latch pin current source is switched on to charge the latc h pin capacitor. at the same time the pfcsense and fbsense soft-start cu rrent sources are switched on. 5. when the latch pin is charged up to 1.35 v and the vinsense pin has reached a level of 0.4 v, the pfc and flyback convertor start switching. 6. with the pfc, the soft-start capacitor connected to pin pfcsense must be charged up to 0.5 v and the voltage on the vosense pin must be greater than 0.4 v. 7. with the flyback controller, the soft-start capacitor co nnected to pi n fbsense must be charged up to 0.5 v and the voltage on the fbctrl pin must be less than 4.5 v. normally, the voltage on the fbctrl pin is al ways less than 4.5 v on the first flyback switching cycle, unless the fbctrl pin is open. when the flyback controller starts, the fbctrl time ou t current source is switched on. 8. when the flyback has reached its nominal output voltage, the v cc supply of the ic is taken over through the aux iliary winding. if the flyback feedback loop signal is missing, time-out protection on the fbctrl pin is triggered and both controllers are switched off, v cc drops to the v th(uvlo) value and the ic continues with step 3 of the start-up cycle. this is the safe restart cycle. fig 2. pfc start condition fig 3. flyback start conditions and latch > 1.35 v pfcsense (soft start) 0.5 v vinsense > 1.15 v vosense > 0.4 v enable pfc 019aac321 and latch > 1.35 v fbsense (soft start) 0.5 v vosense > 1.15 v fbctrl < 0.4 v enable flyback 019aac322
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 9 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller the charge time of the soft-start capacitors is set by choosing their values independently for the pfc and the flyback controller. in this way, it can be realized that the pfc starts before the flyback. 3.3 v cc cycle at safe restar t protection features in safe restart mode the controller goes through steps 3 to 8 as described in section 3.2 . 3.4 mains voltage sensing and brownout the mains input voltage is measured thro ugh the vinsense pin. when the vinsense pin has reached the v start(vinsense) level of 1.15 v, the pfc c an start switching but only if the other start conditions are met as well (see section 3.1 ). as soon as the voltage on pin vinsense drops below the v stop(vinsense) level of 0.89 v, the pfc stops switching. fig 4. start-up sequence at low mains voltage v cc latch protection pfcsense pfcdriver fbsense fbdriver fbctrl vosense v o charging vcc capacitor starting converters normal operation protection restart soft start soft start i hv v start(vinsense) v to(fbctrl) v startup v th(uvlo) v trip v en(latch) v start(fb) vinsense 014aaa156
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 10 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller the flyback however, continues switching unt il the flyback maximum on-time protection, t on(fb)max (40 s) is triggered. when this protection is triggered, the ic stops switching and enters the safe restart mode. the voltage on the vinsense pin must be an average dc value, representing the mains input voltage. the system works optimally wit h a time constant of approximately 150 ms on the vinsense pin. the long time constant on the vinsense pin prevents a fast restart of the pfc after a mains drop-out, therefore the voltage at the vinsense pin is clamped to a level of 100 mv below the v start(vinsense) level to guarantee a fast pfc restart after recovery of the mains input voltage. 3.4.1 discharge of mains input capacitor according to ref. 1 for safety, the x-capacitors in the emc input filt ering must be discharged with a time constant < 1 s. the r to discharge the x-cap in the input filt ering is determined by the replacement value of r1+ r2. in a typical 90 w adapter application with cx1 = 220 nf, the replacement value of r1 + r2 must be smaller than or equal to the following: (1) 3.4.2 brownout voltage adjustment the rectified ac input voltage is measured via r1 and r2. each resistor alternately senses half the sine wave, so both resistors must have the same value. the average voltage sensed at the con nection of r1 and r2 is as follows: fig 5. vinsense circuitry 019aac323 mains inlet vinsense ssl4101 r4 c20 c1 cx1 r3 r1 - + bd1 r2 r v c --- - 1 220 nf ----------------- - 4.55 m ==
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 11 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller (2) the v (ac) brownout rms leve l is calculated as follows: (3) where: v bo is the ac brownout voltage; v stop(vinsense) = 0.89 v with an obtained brown-out threshold (v th(bo) ) of 68 v (ac) and complying with ref. 1 . example values are shown in ta b l e 2 . a value of 3.3 f for capacitor c20, with 47 k at r4, gives the recommended time constant of ~150 ms on the vinsense pin. 3.5 internal otp the ic has an internal overtemperature protec tion (otp) circuit to protect the ic from overheating by overloads on the v cc pin. when the junction temperature exceeds the thermal shutdown temperature, the ic stops sw itching. as long as the otp is active, the v cc capacitor is not recharged fr om the hv mains. the otp circuit is supplied by the hv pin if the v cc supply voltage is not sufficient. otp is a latched protection. 3.6 latch pin the latch pin is a general purpose input pin which can be used to latch both controllers off. the pin sources a bias current i o(latch) of 80 a for the direct connection of the negative temperature coefficient (ntc) resistor. when the voltage on this pin is pulled below 1.25 v, switching of both controllers immediately stops. v cc starts cycling between the v th(uvlo) and v startup , without a restart. switching off and then switching on the mains input voltage triggers the fast latch reset circuit and resets the latch. at start-up, the latch pin must be charged above 1.35 v, before both controllers are enabled. charging of the latch pin starts at v startup . no internal filtering is present at the la tch pin. a 10 nf capacitor must be placed between this pin and the gnd pin to prevent false triggering, also when the latch pin function is not used. table 2. vinsense component values cx1 r1 r2 r3 r4 220 nf 2 m 2m 560 k 47 k 330 nf 1.5 m 1.5 m 820 k 47 k 470 nf 1 m 1m 1.1 m 47 k v avg 22 ---------- vac () rms ? = v bo 22 ---------- v stop vinsense () 2 r1 r2 ? r1 r2 + r4 ------------------- - 1 + ?? ?? ----------------------------------- r3 + ??? =
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 12 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller latching on application overtemperature occurs when the total resistance value of the negative temperature coefficient (ntc) and its series resistor drops below the following: (4) the optocoupler triggers the latch if the driven optotransistor conducts more than 80 a. 3.7 fast latch reset switching off and then switching on the ma ins input voltage, can reset the latched protection. after the mains in put is switched off, the voltage on the vinsense pin drops below v flr (0.75 v). this triggers the fast latch reset circuit, but it does not reset the latched protection. after the ma ins input is switched on, the voltage on the vinsense pin rises again and when the level passes 0.85 v, th e latch is reset. the system restarts again when the v cc pin is charged to v startup . see step 4 of section 3.2 fig 6. usage of the latch pin protection latch ssl4101 019aac324 c19 u4 4 3 1 2 r26 rt r otp v prot latch () i olatch () ------------------------------- 1.25 v 80 a --------------- - 15.6 k ===
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 13 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller 4. pfc description and calculation the pfc operates in quasi-resonant (qr) or discontinuous conduction mode (dcm) with valley detection to reduce the switch on losses. the maximum s witching frequency of the pfc is limited to 380 khz. one or more valleys are skipped, when necessary, to keep the frequency below 380 khz. at low output loads, the pfc is switched off to ensure a high-efficiency and a low no-load stand-by input power. after switch off the bulk elcap voltage drops to v (ac) 2. 4.1 pfc output power and voltage control the pfc of the ssl4101t is on-time controlled, therefore it is not necessary to measure the mains phase angle. the on-time is kept cons tant during the half sine wave to obtain a good power factor (pf) and a class- d mains harmonics r eduction (mhr) see ref. 2 . the pfc output voltage is controlled through the vosense pin. at the vosense pin there is a trans-conductance error amplifier wit h a reference voltage of 2.5 v. the error at the vosense pin is converted with 80 a/v into a current at the pfccomp pin. the voltage at the pfccomp pin, in combination with the voltage at the vinsense pin, determines the pfc on-time. fig 7. pfc on-time control v vinsense v vosense v/i transducer i 2 + - + - v m i dis v - v + v r v s r q s v pfcgate pfc oscillator v osc valley detection v pfcaux voltage comparator ramp oscillator v valley t on limiting circuit i comp compensation network c1 c2 r1 v ref transconductance amplifier current multiplier i 1 i 2 v p cs 014aaa771
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 14 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller to stabilize the pfc control loop, a network wit h one resistor and two capacitors at the pfccomp pin is used. the mathematical equat ion for the transfer function of a boost controller contains the square of the mains in put voltage. in a typical application, this results in a low regulation bandwidth for lo w mains input voltages and a high regulation bandwidth at high input voltages, while at high mains input voltages it can be difficult to meet the mhr requirements. the ssl4101t uses the mains input voltage measured through the vinsense pin to compensate the control loop gain as function of the mains input voltage. as a result the gain is constant over the entire mains input voltage range. the voltage at the vinsense pin must be an average dc value, representing the mains input voltage. the system works optimally wit h a time constant of approximately 150 ms on the vinsense pin. 4.1.1 setting the pfc output voltage the pfc output voltage is set with a resistor divider between the pfc output voltage and the vosense pin. in pfc normal mode, the pfc output voltage is regulated so that the voltage on the vosense pin is equal to v reg(vosense) =2.5v. two resistors of 4.7 m (1 %) can be used for low no-load input power placed between the bulk elcap and the vosense pin. with a resistor value of 4.7 m for r5 and r6 and 60 k to 62 k for r7, a universal mains adapte r will have a pfc output voltage of approximately 380 v to 390 v at high mains and 240 v to 250 v at low mains. the resistor r7 (1 %) between the vosen se pin and ground can be calculated with equation 5 : (5) if the regulated pfc output voltage is 382 v, then: (6) (1) place c4 and r7 as close as possible to the ic. fig 8. pfc output voltage setting vosense ssl4101 c4 (1) pfc stage d1 c3 v o(pfc) r5 r6 r7 (1) 019aac325 r7 r5 r6 + () v reg vosense () v o pfc () v reg vosense () ? () ------------------------------------------------------------------ - = r7 4.7 m 4.7 m + () 2.5 v 382 v 2.5 v ? () --------------------------------------------------------------------- - 62 k 1 % () ==
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 15 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller the function of the capacitor c4 connected to the vosense pin, is to filter noise and to prevent false triggering of the protection circuits, due to mosfet switching noise, mains surge events or esd events. false triggering of the v ovp(vosense) protection can cause audi ble noise and disturbance of the ac mains input current. false triggering of the v th(ol)(vosense) protection causes a safe restart cycle. a time constant of 500 ns to 1 ms, for the vosense pin should be sufficient, resulting in a val ue of 10 nf for capacitor c4. it is advisable to place r7 and c4 as close as possible to the ic between the vosense pin and the ic ground pin. 4.1.2 calculation of the pfc soft-start and soft-stop components the soft-start and soft-stop are implemented through the rc network connected to the pfcsense pin. r ss1 must have a minimum value of 12 k as specified. this to ensure that the voltage v start(soft)pfc of 0.5 v is reached to enable start-up of the pfc. see section 3.1 for start-up description. the total soft-start or soft-stop time is equal to: it is advised to keep the soft-start time of the pfc smaller than the soft-start time of the flyback controller to ensure that the pfc starts before the flyback at initial start-up. it is also advised that the soft-start time is kept within a range of 2 ms to 5 ms. with c8 = 100 nf and r11 = 12 k , the total soft-start time will be 3.6 ms. 4.2 pfc demagnetizing and valley detection the pfc mosfet is switched on after the trans former is demagnetized. internal circuitry connected to the pfcaux pin detects the end of the secondary stroke. it also detects the voltage across the pfc mosfet. the next stroke is started if the voltage across the pfc mosfet is at its minimum to reduce switch ing losses and electromagnetic interference (emi) (valley switching). the maximum switching frequency of the pfc is limited to 380 khz. one or more valleys are skipped, when necessary, to keep the frequency below 380 khz. fig 9. pfc soft-start soft start control ocp 11 pfcsense 0.5 v i startup(soft)pfc 60 a s1 r ss1 c ss1 r sense1 014aaa15 7 t soft s ? tart 3rss1 css1 ? =
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 16 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller if no demagnetization signal is detected on the pfcaux pin, the controller generates a zero current signal (zcs), 50 ms after the last pfc gate signal. if no valley signal is detected on the pfcaux pin, the controller generates a valley signal 4 s after demagnetization was detected. in some applications, the pi filter before the pfc inductor can start oscilla ting when the pfc switching frequency is close to the th ird harmonic of the pi filter resonance frequency. this could lead to false pfc valle y detection. as a result, the pfc can run in continuous conduction mode. false detection can be suppressed by placing a diode between the ic ground and the pfcaux pin. 4.2.1 design of the pfcaux winding and circuit to guarantee valley detection at low ringing amplitudes, the voltage at the pfcaux pin should be set as high as possible, taking into account its absolute maximum rating of 25 v. the number of turns of the pfcaux wi nding can be calculated as follows: (7) where: v pfcaux is the absolute maximum rating of the pfcaux pin and v l(max) is the maximum voltage load across the pfc primary winding. the pfc output voltage at the pfc ovp level determines the maximum voltage across the pfc primary winding and can be calculated with equation 8 : (8) (1) place d27 and r27 close to the ic. fig 10. pfcaux circuitry 019aac326 c1 c2 l1 l2 9 5 7 1 r27 d27 q1 d1 c3 pin pfcaux ssl4101 n a _ max v pfcaux v lmax () ---------------------- n p 25v v lmax () ------------------ n p == v lmax v ovp vosense () v reg vosense () ---------------------------------- vo pfc 2.63v 2.5v -------------- vo pfc ==
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 17 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller when a pfc coil with a higher nu mber of auxiliary turns is us ed, then a resistor voltage divider can be placed between the auxiliary winding and pin pfcaux. the total resistive value of the divider should be less than 10 k to prevent delay in the valley detection due to parasitic capacitance. the polarity of the signal at the pfcaux pin must be reversed compared to the pfc mosfet drain signal. to protect the pfcaux pin against electrical overstress, for example during lighting surge events, it is advised to place a 5 k resistor between the pfc auxiliary winding and this pin. to prevent incorrect valley switching of the pfc due to external disturbance, the resistor should be placed close to the ic. 4.3 pfc protection features 4.3.1 vosense overvoltage protection at start-up, a voltage overshoot can occur at t he boost elcap. this ov ershoot is caused by the relatively slow response of the pfc cont rol loop. the pfc control loop response must be relatively slow to guarantee a good po wer factor and meet the mhr requirements. the overvoltage protection (ovp) at the vosense pin limits the overshoot. when the v ovp(vosense) level of 2.63 v is detected, the pfc mosfet is immediately switched off, regardless of the on-time setting. switching of the mosfet remains blocked until the voltage at the vosense pin drops below 2.63 v again. when the resistor between the vosense pin and ground is open, ovp is also triggered. the peak voltage at the boost elcap generated by the pfc due to an overshoot and limited by the pfc ovp can be calculated with the equation 9 : (9) 4.3.2 vosense open and short pin detection the vosense pin which senses the pfc out put voltage, has integrated protection circuitry to detect an open and short-circuit ed pin. this pin can also sense if one of the resistors in the voltage divider is open. therefore the vosense pin is completely fail-safe. it is not necessary to add an external ovp circuit for the pfc. an internal current source pulls the pin down below the v th(ol)(vosense) detection level of 1.4 v, when the pin is open. at detection of the v th(ol)(vosense) level switching of the pfc mosfet is blocked until the voltage at the vosense pin rises above 0.4 v again. 4.3.3 vinsense open pin detection the vinsense pin which senses the mains input voltage, has an integrated protection circuit to detect an open pin. an internal current source pulls the pin down below the v stop(vinsense) level of 0.89 v, when the pin is open. vo pfc _ peak v ovp vosense () v reg vosense () ----------------------------------- - vo pfc _ nominal ? 2.63v 2.5v -------------- vo pfc _ nominal ? ==
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 18 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller 4.3.4 overcurrent protection (ocp) an overcurrent protection (ocp) limits the maximum current through the pfc mosfet and pfc inductor. the current is measured via a current sense resistor in series with the mosfet source. the mosfet is immediatel y switched off when the voltage at pin pfcsense exceeds the v sense(pfc)max level of 0.52 v. the ocp is a switching cycle-by- switching cycle protection. to avoid false triggering of the pfc ocp by swit ching of the flyback, it is advised to keep a margin of 0.1 v into accoun t. false triggering of the v ovp(vosense) protection can cause disturbance of the ac mains input current. it is also advised that a small capacitor of 100 pf to 220 pf is placed directly at th e pfcsense pin to any suppress external disturbance. the current sense resistor can be calculated using equation 10 : (10) where: i pqr(pfc)max is the maximum pfc peak current at the high load and low mains. the maximum peak current for the pfc operating in quasi-resonant mode can be calculated using equation 11 : (11) where: ? p o(max) is the maximum output power of the flyback ? 1.1 is a factor to compensa te for the dead-time between zero current in the pfc inductor at the end of the secondary stroke and the detection of the first valley in qr mode ? is the expected efficiency of the total controller at maximum output power ? v(ac) min is minimum mains input voltage. 5. flyback descripti on and calculation the flyback of the ssl4101t is a variable freq uency controller that can operate in quasi resonant (qr) or discontinuous conduc tion mode with demagnetization detection and valley switching. the setting of the primary peak current controls the output power; the switching frequency is a result. the primary peak current is set through the voltage at the fbctrl pin and measured back at the fbsense pin with the following relationship: . the flyback controls the operational mode of the pfc. at low out put powers, when the primary peak current, , the pfc is switched off. r ocp pfc () v sense pfc () max v min arg ? ip qr pfc () max --------------------------------------------------------------- - 0.52 v 0.1 v ? ip qr pfc () max ----------------------------------- == ip qr pfc () max 22p imax () 1.1 ?? vac () min ------------------------------------------- - 22 p omax () ----------------- - 1.1 ?? vac () min --------------------------------------------- == v sense fb () 0.75 v fbctrl 1v ? ? ip 0.25 ip _ max
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 19 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller demagnetization of the flyback transformer is detected through pin fbaux, connected to the auxiliary winding. the valley is detected through the hv pin which can be connected to the mosfet drain or to the center tap of the primary winding. the input voltage of the flyback is measured through pin fbaux and used to implement and overpower protection (opp). opp keeps the maximum output power of the flyback controller constant over the input voltage. the flyback has an accurate overvoltage prot ection (ovp) circuit. the overvoltage is measured, through pin f baux. both controllers will be swit ched off in a latc hed protection when an overvoltage is detected. 5.1 flyback output power control an important aspect of the ssl4101t flyback system is, that the setting of the primary peak current controls the output power. the sw itching frequency is a result of external application parameters and internal ic parameters. external application parameters are the tran sformer turns ratio, the primary inductance, the drain source capacitance, the input voltage, the output voltage and the feedback signal from the control loop. in ternal ic parameters are the o scillator setting, the setting of the peak current and the detection of demagnetization and valley. the output power of flyback can be described with equation 12 : (12) at initial start-up, the flyback controller always starts at maximum output power. the flyback controller will go thr ough the three operation modes from maximum to minimum output power, as shown figure 11 . at maximum output power, limited by the flyback current sense resistor, the flyback controller operates in qu asi-resonant (qr) mode. the next primary switching cycle starts at detection of the first valley. fig 11. operation modes flyback p o 1 2 -- - lp ip 2 fs ?? ?? = discontinuous with valley switching quasi resonant pfc off frequency reduction f sw(fb)max output power switching frequency 0 pfc on
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 20 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller by reducing the peak current, the output pow er is reduced and as a result the switching frequency increases. when t he maximum flyback switching fr equency is reached and the output power still has to be reduced, the flyback goes fr om qr into dcm with valley switching. in dcm, the output power is reduced by furt her reduction of the peak current and at the same time skipping of one or more valleys. in this mode, the switching frequency is kept constant. the exact switching frequency howeve r, depends on the detection of the valley but will never be higher as the maximum frequency. the minimum flyback peak current: . at this point the flyback controller enters the frequency reduction mode. in the frequency reduction mode the peak current is kept constant. increasing the off time reduces the output power. it is advised to place a 10 nf noise filter ca pacitor (c15) as close as possible to the fbctrl pin to avoid disturbance of the flyback by switching of the pfc mosfet. 5.1.1 calculation of the flyback current sense resistor the current sense resistor r ocp(fb) can be calculated using equation 13 : (13) the peak current can be calculated for the fl yback controller operating in quasi-resonant mode using equation 14 : (14) where: ? p o(max) is the maximum output power of the flyback controller ? 1.1 is a factor that compensates for the dead time between zero current in the flyback transformer at the end of the secondary stro ke and the detection of the first valley in qr mode; ? is the expected efficiency of th e flyback at maximum output power ? v (dc) is the bulk elcap voltage ? v o is the output voltage ? np is the number of primary turns of the flyback transformer ? ns is the number of secondary turns of the flyback transformer. 5.1.2 calculation of the flyback soft-start components the soft-start is implemented through the rc network at pin fbsense. r ss1 must have a minimum value of 12 k as specified. this to ensure that the voltage v start(soft)pfc of 0.5 v is reached to enable start-up of the flyback. see section 3.1 for start-up description. the total soft-start or soft-stop time is equal to . ip _ min 0.25 ip _ max = r ocp fb () v sense fb () max ip qr fb () max ------------------------------ - 0.52 v ip qr fb () max --------------------------- - == ip qr fb () max 2p omax () 1.1 ? vdc () --------------------------------- vdc () np ns ------ - v o ? + np ns ------ - v o ? ------------------------------------------- - = t soft - start 3rss css ? =
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 21 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller it is advisable to make the soft-start time for the flyback larger than the soft-start time of the pfc, to make sure that the pfc starts befo re the flyback at initial start-up. it is also advisable to keep the soft-start time in a range of 5 ms to 10 ms. with c10 = 220 nf and r16 = 12 k the total soft-start time will be 8 ms. 5.2 flyback converter protection circuits 5.2.1 short-circuit on the fbctrl pin if the pin is shorted to ground, switching of the flyback controller is inhibited. this situation is equal to the minimum or a no output power situation. 5.2.2 open the fbctrl pin as shown in figure 12 , the fbctrl pin is connected to a 3.5 v internal voltage source via an internal 3 k resistor. when the voltage on pin fbctrl is above 2.5 v, this connection is disabled and the fbctrl pin is biased with an internal 30 a current source. when the voltage on the fbctrl pin rises above v to(fbctrl) of 4.5 v a fault is assumed. switching of the flyback (and also the pfc) is blocked and the controller will enter the safe restart mode. an internal switch pulls the fbctrl pin do wn when the flyback convertor is disabled. 5.2.3 time-out flyback control-loop a time-out function can be realized to protect for an output short-circuit at initial start-up or for an open control loop situation. this can be done by placing a resistor in series with a capacitor between the fbctrl pin and ground (see figure 12 ). above 2.5 v, the switch in series with the 3 k resistor is open and pin fbctrl (and thus the rc combination) is biased with a 30 a current source. when the voltage on fbctrl pin rises above 4.5 v, switching of the flyback controller and the pfc is blocked causing the controller to enter the safe restart mode. the capacitor can be used to set the time delay to reach 4.5 v at the fbctrl pin. the resistor is necessary to separate the relatively large time-out capacitor from the control loop response. it is advised to use a resistor of at least 30 k . the resistor however, will also influence the charge time of the capacitor. the time-out time t to can be calculated using equation 15 : (15) otherwise the capacitor can be calculated using equation 16 : (16) or the resistor can be calculated using equation 17 : (17) t to c to v to fbctrl () i 0 fbctrl () r to ? () ? () ? i o fbctrl () ------------------------------------------------------------------------------------------------ = c to i o fbctrl () t to ? v to fbctrl () i o fbctrl () r to ? () ? ------------------------------------------------------------------------------- - = r to v to fbcrtl () i ofbcrtl () ----------------------------- t to c to ------- - ? =
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 22 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller a t to of 37 ms in combination with a c to of 330 nf leads to a resistor value of: (18) when the time-out protection is not required, placing a resistor of 100 k between pin fbctrl and ground can disable the time-out protection. 5.2.4 overvoltage protection flyback the ic has an internal overvoltage protec tion (ovp) circuit, which switches off both controllers when an overvoltage is detected at the flyback output, by a latched protection. the ic can detect an overvoltage in a seco ndary winding of the flyback controller by measuring the voltage at the auxiliary winding during the secondary stroke. a series resistor between the auxiliary winding and the fbaux pin co nverts this voltage to a current on the fbaux pin. a. circuit diagram b. timing diagram fig 12. time-out protection r to 4.5v 30 a ------------- 37ms 330nf --------------- - ? 37.9k 39k == 014aaa049 fbctrl 2.5 v 4.5 v 30 a 3 k 3.5 v time-out 014aaa05 0 4.5 v 2.5 v v fbctrl output voltage intended output voltage not reached within time-out time. intended output voltage reached within time-out time. restart
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 23 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller at a current i ovp(fbaux) of 300 a on the fbaux pin, the ic detects an overvoltage. an internal integrator filters noise and voltage sp ikes. the output of the integrator is used as an input for an up-down counter. the counter has been added as an extra filter to prevent false ovp detection which might occur during esd or lightning events. if the integrator detects an overvoltage, the counter increases its value by one. if another overvoltage is detected during the next switch ing cycle, the counter increases its value by one again. if no over voltage is detected during the ne xt switching cycle, the counter will subtract its value by two (the minimum value is 0). if the value reaches 8, the ic assumes a true overvoltage and activates the latched protection. both controllers are immediately switched off and v cc starts cycling between the v th(uvlo) and v startup , without a restart. switching the mains input voltage off and then on triggers the fast latch reset circuit and resets the latch. the ovp level can be set by the resistor r ovp : (19) where: ? n s is the number of turns on the secondary winding ? n aux is the number of turns on the auxilia ry winding of the flyback transformer ? v clamp(fbaux) is the positive clamp-voltage of the fbaux pin. ? v f(d23a) is the forward voltage of d23a at a current of 300 a for the calculation of the v o(ovp) level the tolerances on i ovp(fbaux) have to be taken into account, this to avoid triggering of the ovp during normal operation. fig 13. flyback ovp and opp circuit aux sec prim r ovp = r23 1 2 4 pin vcc pin fbaux ssl4101 r opp = r23 + r23a d10 c13 d5 d23a t1 r23 019aac327 r ovp n aux n s ------------- v oovp () ?? ?? v clamp fbaux () v fd23a () ? ? i ovp fbaux () ------------------------------------------------------------------------------------------------------------------ - n aux n s ------------- v oovp () ?? ?? 0.7 typ () v fd23a () ? ? 300 a typ () ------------------------------------------------------------------------------------------------ ==
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 24 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller 5.2.5 overpower protection (opp) in a quasi-resonant flyback, the maximum outp ut power is dependent on the (mains) input voltage. opp is implemented to compensate. during the primary stroke of the flyback the mains voltage is sensed by measuring the current drawn from pin fbaux. with a resistor connected between the flyback auxiliary winding and pin fbaux, the voltage at the aux iliary winding is converted into a current i fbaux (see figure 13 ). the ic is using the current information to reduce the setting of the maximum flyback peak current measured through pin fbsense. see figure 14 for the limitation of the maximum v fbsense level as a function of i fbaux . the total opp resistance determines the i fbaux current during the primary stroke of the flyback and consists of r23 + r23a (see figure 13 ). first, the ovp resistor r23 has to be calculated before the remaining part of the opp resistor r23a can be calculated. the value of r23a can be calculated by: (20) 6. summary of calculations see figure 1 application schematic for component reference numbers. fig 14. operation modes flyback i fbaux ( a) ? 400 ? 360 0 ? 100 ? 300 ? 200 014aaa096 0.4 0.5 0.6 v fbsense (v) 0.3 0.52 0.37 r23a na np ------ - v opfc () low ? v clamp fbaux () ? i start opp () fbaux -------------------------------------------------------------------------------- na np ------ - 240 v 0.8 v ? ? 100 a --------------------------------------------- - r ovp ? ==
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 25 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller 7. pcb layout considerations 8. references [1] iec-60950 ? chapter 2.1.1.7 ?discharge of capacitors in equipment? [2] iec61000-3-2 ? limits for harmonic current emissions
an11054 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 13 may 2011 26 of 27 nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller 9. legal information 9.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 9.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 9.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. greenchip ? is a trademark of nxp b.v.
nxp semiconductors an11054 greenchip iii+ ssl4101 integrated pfc and flyback controller ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 13 may 2011 document identifier: an11054 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 10. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 the ssl4101 greenchip iii+ controller . . . . . . 3 1.2.1 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.2 system features . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.3 pfc features . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.4 flyback features . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 application schematic . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 system description and calculation. . . . . . . . . 8 3.1 pfc and flyback start conditions . . . . . . . . . . . 8 3.2 start-up sequence. . . . . . . . . . . . . . . . . . . . . . . 8 3.3 v cc cycle at safe restart prot ection features . . 9 3.4 mains voltage sensing and brownout . . . . . . . . 9 3.4.1 discharge of mains input capacitor. . . . . . . . . 10 3.4.2 brownout voltage adjustment . . . . . . . . . . . . . 10 3.5 internal otp . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 latch pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.7 fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . 12 4 pfc description and calculation . . . . . . . . . . 13 4.1 pfc output power and voltage control . . . . . . 13 4.1.1 setting the pfc output voltage. . . . . . . . . . . . 14 4.1.2 calculation of the pfc soft-start and soft-stop components . . . . . . . . . . . . . . . . . . . 15 4.2 pfc demagnetizing and valley detection . . . . 15 4.2.1 design of the pfcaux winding and circuit . . 16 4.3 pfc protection features . . . . . . . . . . . . . . . . . 17 4.3.1 vosense overvoltage protection . . . . . . . . 17 4.3.2 vosense open and short pin detection . . . . 17 4.3.3 vinsense open pin detection . . . . . . . . . . . . 17 4.3.4 overcurrent protection (ocp) . . . . . . . . . . . . 18 5 flyback description and calculation . . . . . . . 18 5.1 flyback output power control . . . . . . . . . . . . . 19 5.1.1 calculation of t he flyback current sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.2 calculation of the flyback soft-start components . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 flyback converter protection circuits . . . . . . . 21 5.2.1 short-circuit on the fbctrl pin. . . . . . . . . . . 21 5.2.2 open the fbctrl pin . . . . . . . . . . . . . . . . . . 21 5.2.3 time-out flyback control-loop . . . . . . . . . . . . . 21 5.2.4 overvoltage protection flyback . . . . . . . . . . . . 22 5.2.5 overpower protection (opp) . . . . . . . . . . . . . 24 6 summary of calculations . . . . . . . . . . . . . . . . 24 7 pcb layout considerations . . . . . . . . . . . . . . . 25 8 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 legal information . . . . . . . . . . . . . . . . . . . . . . 26 9.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.3 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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